The present invention relates to the control of an integrated memory circuit to provide active termination of a data bus. More particularly, the invention provides a system to control the active termination required for dynamic random access memory (DRAM) devices.
Modern systems strive to efficiently utilize computer memory in a way which increases speed and optimizes data transfer. This requires specialized techniques for controlling the reading and writing of information from and to memory, such as dynamic random access memory (DRAM), particularly with respect to high speed memory devices.
One proposed technique for controlling read/write operations in high speed DRAM devices divides DRAM memory devices into ranks which are turned on or off for data read/write operations via an active termination control signal supplied by a memory controller. The active termination control signal determines which rank of memory is being read from or written to. In these proposals, an xe2x80x98onxe2x80x99 signal enables a particular DRAM memory device to be written to and an xe2x80x98offxe2x80x99 signal enables a DRAM memory device to be read. For double sided memory modules which have a rank of memory on each side of the module, this requires two such control signals for each module. In other words, these proposals require at least one hard-wired active termination control signal for the front side of a memory module (Rank 0) and a separate hard-wired active termination control signal for the back side of a memory module (Rank 1).
Problems with such configurations include difficulty for the controller circuitry to hand off between reading and writing to/from different sides of modules. Furthermore, having two active termination control signals per module requires the use of two hard-wired active termination control signal paths per module and on the bus. This leads to read-write lag time inefficiencies between the controller circuitry and actual memory devices.
There is needed, therefore, a simple and inexpensive method of controlling reading and writing to different ranks of memory on a module.
The present invention provides a simplified active termination control technique for each memory module which utilizes: (i) one controller-generated hard-wired active termination control signal per dual sided module which causes the data devices on both sides of the module to transition to an active termination state as a rank and (ii) a wired-OR signal path which causes a read operation at memory devices on either side of the module to disable the active termination control signal for memory devices on both sides of the module. Both the singular active termination control signal per module and the wired-OR signal path decrease lag time inefficiencies between the controller circuitry and read-write operations to memory ranks on a module.
These and other advantages and features of the invention will be more clearly understood from the following detailed description of the invention which is presented in conjunction with the accompanying drawings.